1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a structure of a Metal Insulator Metal (hereinafter referred to as MIM) capacitor element.
2. Description of the Background Art
In recent years, demand for a capacitor element in an analog circuit having a high precision and a high capacitance has increased. Conventionally, a gate capacitor element or a PIP (Poly Si Insulator Poly Si) capacitor element has been mounted in an analog circuit as a capacitor element. However, the structures of these capacitor elements have problems such as (i) high electrode resistance and (ii) dependence of capacitance value on voltage due to change in film thickness of the depletion layer and, therefore, they are not appropriate as high precision capacitor elements. In addition, in contrast to a manufacturing process for a semiconductor device that does not include a PIP capacitor element, an extra step of heat treatment, which affects the characteristics of a transistor and a resistance element with a high precision, becomes necessary in a manufacturing process for a semiconductor device having a PIP capacitor element and, therefore, it has been difficult to control the manufacturing process by taking these characteristics into consideration.
On the other hand, Metal Insulator Metal (hereinafter referred to as MIM capacitor elements disclosed in Japanese Patent Laying-Open No. 2000-228497, Japanese Patent Laying-Open No. 2000-101023, U.S. Pat. No. 5,926,359 and the like have advantages such as (i) reduced resistance of electrodes, (ii) no dependence of capacitor value on voltage due to a depletion layer, and (iii) an extra heat treatment is unnecessary at the time of the formation of an MIM structure because the upper layer electrodes and the lower layer electrodes have metal structures, so that MIM capacitor elements have come to be utilized in place of PIP capacitor elements in analog circuits.
In the case that an MIM capacitor element is used in an analog circuit, however, it is necessary to achieve optimization of the structure and of the manufacturing process of the MIM capacitor element concerning the enhancement of reliability (lifetime) and performance.
Here, the structure of a semiconductor device having a conventional MIM capacitor element will be described in reference to FIG. 20. A lower layer electrode layer 8 is formed on top of an interlayer insulating film 1 and a dielectric film 9 as well as an upper layer electrode layer 10 having a predetermined form are provided on top of this lower layer electrode layer 8 in the structure of the semiconductor device. Lower layer electrode layer 8 has a TiN layer 2, an AlCu layer 3 and a TiN/Ti layer 4. In addition, upper layer electrode layer 10 has a TiN layer 5, an AlCu layer 6 and a TiN/Ti layer 7.
A reflection prevention film 12 and an interlayer insulating film 13 are provided in the upper surface region of upper layer electrode layer 10 and of lower layer electrode layer 8. In addition, via holes 14 reaching to upper layer electrode layer 10 are provided in interlayer insulating film 13, and wire layers 15 are formed in these via holes 14.
In the semiconductor device of the above described structure, a problem can be cited wherein a leak current is generated, as indicated by the circled regions of FIG. 20, between lower layer electrode layer 8 and upper layer electrode layer 10 via reflection prevention film 12 in the case that a conductive material such as a plasma SiON film, for example, is used as reflection prevention film 12.
An object of the present invention is to achieve an improvement in the structure of an MIM capacitor element and to achieve a further improvement in the manufacturing process of an MIM capacitor element in a semiconductor device wherein the MIM capacitor element is used, to thereby make it possible to enhance reliability (lifetime) and performance of the MIM capacitor element.
A semiconductor device according to the present invention is a semiconductor device having a capacitor element formed of a lower layer electrode layer, a dielectric layer provided on the lower layer electrode layer and an upper layer electrode layer provided on the dielectric layer, which are layered, and includes an insulating film for covering the upper layer electrode layer and a reflection prevention film provided to the upper layer electrode layer with the insulating film intervened therebetween.
According to the semiconductor device, an insulating film is provided as a leak guard covering the upper layer electrode layer between the upper layer electrode layer and the reflection prevention film and, therefore, a region where the upper layer electrode layer and the reflection prevention film make contact with each other is not formed. As a result, it becomes possible to completely prevent the generation of a leak current between the upper layer electrode layer and the lower layer electrode layer. As a result, it becomes possible to improve the reliability and the performance of the operational characteristics of the semiconductor device provided with an MIM capacitor element having a lower layer electrode layer, a dielectric layer and an upper layer electrode layer.
In addition, in the semiconductor device, the upper layer electrode layer is preferably provided so as to have a width that is smaller than the width of the dielectric layer. The insulating film is provided so as to cover the exposed edge surfaces of the upper layer electrode layer and the upper surface region. The reflection prevention film is provided so as to cover the edge surface regions of the insulating layer and the edge surface regions of the dielectric layer. In addition, in the present invention, the reflection prevention film is more preferably provided so as to also cover the upper surface region of the insulating layer.
With this configuration, the edge surface regions, as well as the upper surface region, of the upper layer electrode layer are covered with an insulating film as a leak guard and a reflection prevention film is provided on top of this insulating film, thereby it becomes possible to completely prevent the occurrence of a leak current between the upper layer electrode layer and the lower layer electrode layer.
In addition, in accordance with a semiconductor device according to another aspect of the present invention, the reflection prevention film is provided in only the upper surface region of the insulating layer. With this configuration, the upper surface region of the upper layer electrode layer is covered with an insulating film as a leak guard and a reflection prevention film is provided on the insulating film, thereby it becomes possible to completely prevent the generation of a leak current between the upper layer electrode layer and the lower layer electrode layer.
In addition, in the semiconductor device, the upper layer electrode layer is preferably provided so as to have a width that is approximately the same as the width of the dielectric layer. The insulating layer is provided so as to cover the edge surface regions and the upper surface region of the upper layer electrode layer as well as the edge surface regions of the dielectric layer. The reflection prevention film is provided on the lower layer electrode layer so as to be isolated, by means of the insulating layer, from the upper layer electrode layer and from the dielectric layer.
With this configuration, the edge surface regions of the upper layer electrode layer are covered with an insulating film as a leak guard and a reflection prevention film is provided with this insulating film intervened therebetween, thereby it becomes possible to completely prevent the generation of a leak current between the upper layer electrode layer and the lower layer electrode layer.
A common photomask is utilized for patterning the upper layer electrode layer and for patterning the insulating film as well as the dielectric layer, thereby it becomes possible to achieve a reduction in manufacturing cost.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.